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TMS320DM643 Datasheet(PDF) 144 Page - Texas Instruments |
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TMS320DM643 Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 162 page  www.ti.com MRCLK (Input) 1 2 MRXD3−MRXD0, MRXDV, MRXER (Inputs) 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007 MRXD3–MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3–MRXD0 timing must be met during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on the falling edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00–01). Figure 5-61. EMAC Receive Interface Timing Table 5-67. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (1) (see Figure 5-62) –500 –600 NO. UNIT MIN MAX 1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 25 ns (1) Transmit selected signals include: MTXD3–MTXD0, and MTXEN. MTXD3–MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge. Figure 5-62. EMAC Transmit Interface Timing 144 DM643 Peripheral Information and Electrical Specifications Submit Documentation Feedback |
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