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IS25LP02GJ-RHLA3 Datasheet(PDF) 166 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LP02GJ-RHLA3
Descripción Electrónicos  SERIAL FLASH MEMORY 166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  182 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP02GJ-RHLA3 Datasheet(HTML) 166 Page - Integrated Silicon Solution, Inc

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IS25LP02GJ
IS25WP02GJ
Integrated Silicon Solution, Inc.- www.issi.com
166
Rev.A
10/02/2025
8.67 WRITE VDLR OPERATION (WRVDLR, 4Ah)
Before the Write VDLR (WRVDLR) command can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded
successfully, the device will set the Write Enable Latch (WEL) to enable the WRVDLR operation.
The WRVDLR command (4Ah) is entered by shifting the instruction and data byte on SI.
CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WRVDLR
command is not executed. As soon as CE# is driven to the logic high state, the WRVDLR operation is initiated
with no delays.
Figure 8.145 WRVDLR Sequence In SPI Mode
Instruction = 4Ah
CE#
SCK
SI
SO
Data In
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
7
3
2
1
0
6
5
4
High Impedence
Figure 8.146 WRVDLR Sequence In QPI Mode
4Ah
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In



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