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STM32H533CE Datasheet(PDF) 166 Page - STMicroelectronics |
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STM32H533CE Datasheet(HTML) 166 Page - STMicroelectronics |
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166 / 231 page  Electrical characteristics STM32H533xx 166/231 DS14539 Rev 1 5.3.19 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 86 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20, with the following configuration: 5.3.20 DCMI interface characteristics Unless otherwise specified, the parameters given in Table 87 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits • Capacitive load CL = 30 pF • Measurement points done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling VOS0 selected Table 86. Delay block characteristics Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 640 1040 1760 ps t∆ Unit delay - 38 44 54 ps Table 87. DCMI characteristics(1) Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 - DCMI_PIXCLK Pixel clock input - 100 MHz DPIXEL Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2.5 - ns th(DATA) Data hold time 2 - tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times 2.5 - th(HSYNC), th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times 1.5 - 1. Evaluated by characterization - Not tested in production. |
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