DP83867CS datasheet(115/129 Pages) TI2

No. de pieza	DP83867CS

Descripción Electrónicos	DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver

PDF	129 Pages

Scroll/Zoom	100%

Fabricante Electrónico	TI2 [Texas Instruments]

Página de inicio	https://www.ti.com

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8.4.1.5 PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a 4-layer PCB can be used. However a 6-

layer board is recommended. See Figure 8-12 for the recommended layer stack ups for 4, 6 and 8-layer boards.

These are recommendations not requirements, other configurations can be used as per system requirements.

Figure 8-12. Recommended Layer Stack Up

Within a PCB, a desirabled can be to run traces using different methods, microstrip vs. stripline, depending on

the location of the signal on the PCB. For example, the opportunity can be desirable to change layer stacking

where an isolated chassis ground plane is used. Figure 8-13 illustrates alternative PCB stacking options.

Figure 8-13. Alternative Layer Stack Up

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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DP83867CS Datasheet(PDF) 115 Page - Texas Instruments