STPM098C datasheet(109/110 Pages) STMICROELECTRONICS

109 / 110 page

Figure 54.

Single phase negative over-current monitor timing diagram - SLOW_RETRY = 1 ..................... 65

Figure 55.

Phase current overbalance timing diagram ................................................ 66

Figure 56.

Current sum overcurrent timing diagram ................................................. 68

Figure 57.

Feedback disconnection simplified block diagram ........................................... 69

Figure 58.

FDM timing diagram ............................................................... 70

Figure 59.

Loop controller simplified block diagram.................................................. 70

Figure 60.

Voltage setpoint definition simplified block diagram .......................................... 73

Figure 61.

DVID transition timing diagram ........................................................ 75

Figure 62.

Load-line functionality simplified behavior................................................. 76

Figure 63.

Converted simplified block diagram ..................................................... 78

Figure 64.

Closed loop transfer function ......................................................... 78

Figure 65.

Digital compensator simplified block diagram .............................................. 79

Figure 66.

PWM SSM modulation operation ...................................................... 82

Figure 67.

Phase current balancing simplified block diagram ........................................... 83

Figure 68.

T_on time, steady state ............................................................. 84

Figure 69.

T_on time with MULTI_PULSE_STRAT = 0x00 ............................................. 84

Figure 70.

T_on time with MULTI_PULSE_STRAT = 0x01 ............................................. 84

Figure 71.

T_on time with MULTI_PULSE_STRAT = 0x02 ............................................. 85

Figure 72.

T_on time with MULTI_PULSE_STRAT = 0x03 ............................................. 85

Figure 73.

DPS timing diagram ............................................................... 87

Figure 74.

DPM configuration efficiency-load current - Example 1........................................ 89

Figure 75.

DPM configuration efficiency-load current - Example 2........................................ 90

Figure 76.

Zero-current detection simplified block diagram............................................. 91

Figure 77.

ADE activation timing diagram ........................................................ 92

Figure 78.

ADE timing diagram with masking delay.................................................. 92

Figure 79.

PMBus™ AC characteristics timing diagram ............................................... 93

Figure 80.

Safe states activation paths .......................................................... 96

Figure 81.

Damage protected activation simplified structure............................................ 97

Figure 82.

Reference application circuit.......................................................... 99

Figure 83.

VFQFN48+4L (7x7x0.9 mm exp. pad down) package outline .................................. 101

STPM098C

List of figures

DS14440 - Rev 1

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