L9908 datasheet(151/152 Pages) STMICROELECTRONICS

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Figure 54.

Free running sampling timing diagram - non-zero current + auto-triggering .......................... 80

Figure 55.

Free running sampling timing diagram - non-zero current + auto-triggering, latency to CSOn ............. 80

Figure 56.

Free running sampling timing diagram - non-zero current + command edge-triggering .................. 81

Figure 57.

Free running sampling timing diagram - zero current (offset) + auto-triggering........................ 81

Figure 58.

Free running sampling timing diagram - zero current (offset) + command edge-triggering ................ 82

Figure 59.

T&H sampling timing diagram - non-zero current + auto-triggering................................ 83

Figure 60.

T&H sampling timing diagram - zero current (offset) + auto-triggering ............................. 84

Figure 61.

T&H sampling timing diagram - non-zero current + command edge-triggering ........................ 84

Figure 62.

T&H sampling timing diagram - zero current (offset) + command edge-triggering...................... 85

Figure 63.

D/A conversion simplified block diagram ................................................. 86

Figure 64.

A/D-D/A chain accuracy block diagram .................................................. 88

Figure 65.

OFF State diagnosis simplified block diagram.............................................. 90

Figure 66.

OFD currents in motor phases ........................................................ 92

Figure 67.

OFD enabling and masking time start - IPU example ......................................... 92

Figure 68.

OFD masking and deglitch filtering - LSn_OFD example ...................................... 93

Figure 69.

OFD masking and deglitch filtering - LSn_OFD example with multiple glitches ....................... 93

Figure 70.

ON State Diagnosis simplified block diagram .............................................. 95

Figure 71.

OND blanking and filtering (VDS_LSn example), multiple fault .................................. 96

Figure 72.

OND blanking and filtering (VDS_LSn example), single fault.................................... 97

Figure 73.

Off State Diagnosis block diagram...................................................... 98

Figure 74.

Phase voltage feedback behavior ...................................................... 99

Figure 75.

Actuation Timer simplified block diagram ................................................ 100

Figure 76.

Actuation Timers timing diagram on ACT (positive & negative polarity)............................ 101

Figure 77.

Ground pins inter-connection ........................................................ 102

Figure 78.

Temperature monitor ADC characteristics ............................................... 103

Figure 79.

Junction temperature ranges ........................................................ 104

Figure 80.

SPI connection modes "a" star connection (supported) "b" daisy-chain connection (not supported) ........ 105

Figure 81.

SPI timing diagram ............................................................... 105

Figure 82.

SPI Write-Read operation .......................................................... 108

Figure 83.

SPI Read-Read operation .......................................................... 108

Figure 84.

SPI Clear on Read operation ........................................................ 109

Figure 85.

Watchdog timer simplified block diagram ................................................ 130

Figure 86.

WDT operation – Overflow timer failure ................................................. 131

Figure 87.

Watchdog command order sequence................................................... 132

Figure 88.

WDT operation – Word sequence failure ................................................ 133

Figure 89.

WDT operation – WDT reset after overflow timer failure ...................................... 134

Figure 90.

Application circuit, 12 V/24 V systems .................................................. 135

Figure 91.

Application circuit, 48 V systems ...................................................... 136

Figure 92.

TQFP48 (7x7x1 mm exp. pad down) package outline ....................................... 139

Figure 93.

Suggested PCB landpattern ......................................................... 141

L9908

List of figures

DS13546 - Rev 5

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