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ADC32RF44IRMPR Datasheet(PDF) 116 Page - Texas Instruments |
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ADC32RF44IRMPR Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 135 page ![]() Power Supplies RESET SEN t1 t2 t3 116 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 10.1.2 Hardware Reset Timing information for the hardware reset is shown in Figure 231 and Table 119. Figure 231. Hardware Reset Timing Diagram Table 119. Hardware Reset Timing Information MIN TYP MAX UNIT t1 Power-on delay from power-up to active high RESET pulse 1 ms t2 Reset pulse duration: active high RESET pulse duration 1 µs t3 Register write delay from RESET disable to SEN active 100 ns |
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