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PIC12LF1501 Datasheet(PDF) 165 Page - Microchip Technology |
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PIC12LF1501 Datasheet(HTML) 165 Page - Microchip Technology |
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165 / 352 page  2011-2015 Microchip Technology Inc. DS40001607D-page 165 PIC16(L)F1503 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP inter- rupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. After the device returns to Run mode, the mod- ule will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 PIE1 TMR1GIE ADIE — —SSP1IE — TMR2IE TMR1IE 65 PIR1 TMR1GIF ADIF — — SSP1IF — TMR2IF TMR1IF 68 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 158* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 204 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 206 SSP1STAT SMP CKE D/A P S R/W UA BF 203 TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 98 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. * Page provides register information. Note 1: Unimplemented, read as ‘1’. |
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