PIC12LF1501 datasheet(131/352 Pages) MICROCHIP

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DS40001607D-page 131

PIC16(L)F1503

FIGURE 17-2:

SINGLE COMPARATOR

17.2

Comparator Control

Each comparator has two control registers: CMxCON0

and CMxCON1.

The CMxCON0 registers (see Register 17-1) contain

Control and Status bits for the following:

• Enable

•Output selection

• Output polarity

• Speed/Power selection

• Hysteresis enable

• Output synchronization

The CMxCON1 registers (see Register 17-2) contain

Control bits for the following:

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

17.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

17.2.2

COMPARATOR POSITIVE INPUT

SELECTION

Configuring the CxPCH<1:0> bits of the CMxCON1

analog pin to the non-inverting input of the comparator:

• CxIN+ analog pin

• DAC1_output

• FVR_buffer2

•VSS

See Section 13.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Section 16.0 “5-Bit Digital-to-Analog Converter

(DAC) Module”

for more information on the DAC input

signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

17.2.3

COMPARATOR NEGATIVE INPUT

SELECTION

The CxNCH<2:0> bits of the CMxCON0 register direct

one of the input sources to the comparator inverting

input.

17.2.4

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

The

synchronous

comparator

output

signal

(CxOUT_sync) is available to the following peripheral(s):

• Configurable Logic Cell (CLC)

• Analog-to-Digital Converter (ADC)

•Timer1

The

asynchronous

comparator

output

signal

(CxOUT_async) is available to the following peripheral(s):

• Complementary Waveform Generator (CWG)

–

VIN+

VIN-

Output

VIN+

VIN-

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

Note:

To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

Note 1:

The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting

the CxON bit of the CMxCON0 register

has no impact on the port override.

The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

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