PIC12LF1501 datasheet(237/352 Pages) MICROCHIP

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DS40001607D-page 237

PIC16(L)F1503

25.0

COMPLEMENTARY WAVEFORM

GENERATOR (CWG) MODULE

The Complementary Waveform Generator (CWG)

produces a complementary waveform with dead-band

delay from a selection of input sources.

The CWG module has the following features:

• Selectable dead-band clock source control

• Selectable input sources

• Output enable control

• Output polarity control

• Dead-band control with independent 6-bit rising

and falling edge dead-band counters

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

- Auto-shutdown pin override control

25.1

Fundamental Operation

The CWG generates two output waveforms from the

selected input source.

The off-to-on transition of each output can be delayed

from the on-to-off transition of the other output, thereby,

creating a time delay immediately where neither output

is driven. This is referred to as dead time and is covered

in Section 25.5 “Dead-Band Control”. A typical

operating waveform, with dead band, generated from a

single input signal is shown in Figure 25-2.

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. This is

referred to as auto-shutdown and is covered in Section

25.9 “Auto-Shutdown Control”

25.2

Clock Source

The CWG module allows the following clock sources

to be selected:

• Fosc (system clock)

• HFINTOSC (16 MHz only)

The clock sources are selected using the G1CS0 bit of

the CWGxCON0 register (Register 25-1).

25.3

Selectable Input Sources

The CWG generates the output waveforms from the

input sources in Table 25-1.

The input sources are selected using the GxIS<2:0>

bits in the CWGxCON1 register (Register 25-2).

25.4

Output Control

Immediately after the CWG module is enabled, the

complementary drive is configured with both CWGxA

and CWGxB drives cleared.

25.4.1

OUTPUT ENABLES

Each CWG output pin has individual output enable

control. Output enables are selected with the GxOEA

and GxOEB bits of the CWGxCON0 register. When an

output enable control is cleared, the module asserts no

control over the pin. When an output enable is set, the

override value or active PWM waveform is applied to

the pin per the port priority selection. The output pin

enables are dependent on the module enable bit,

GxEN. When GxEN is cleared, CWG output enables

and CWG drive levels have no effect.

25.4.2

POLARITY CONTROL

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active-high. Clearing the output

polarity bit configures the corresponding output as

active-low. However, polarity does not affect the

override levels. Output polarity is selected with the

GxPOLA and GxPOLB bits of the CWGxCON0 register.

TABLE 25-1:

SELECTABLE INPUT

SOURCES

Source Peripheral

Signal Name

Comparator C1

C1OUT_sync

Comparator C2

C2OUT_sync

PWM1

PWM1_out

PWM2

PWM2_out

PWM3

PWM3_out

PWM4

PWM4_out

NCO1

NCO1_out

CLC1

LC1_out

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