PIC12LF1501 datasheet(195/352 Pages) MICROCHIP

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DS40001607D-page 195

PIC16(L)F1503

FIGURE 21-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

21.6.10

SLEEP OPERATION

While in Sleep mode, the I2C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

21.6.11

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

21.6.12

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I2C bus may

be taken when the P bit of the SSPxSTAT register is

set, or the bus is idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In Multi-Master mode, the SDAx line must be monitored

for arbitration to see if the signal level is the expected

output level. This check is performed by hardware with

the result placed in the BCLxIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

21.6.13

MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDAx pin, arbitration takes place when the master

outputs a ‘1’ on SDAx, by letting SDAx float high and

another master asserts a ‘0’. When the SCLx pin floats

high, data should be stable. If the expected data on

SDAx is a ‘1’ and the data sampled on the SDAx pin is

‘0’, then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLxIF and reset

the I2C port to its Idle state (Figure 21-32).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDAx and SCLx lines are deasserted and

the SSPxBUF can be written to. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I2C bus is free, the user can resume communica-

tion by asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDAx and SCLx lines are deas-

serted and the respective control bits in the SSPxCON2

lision Interrupt Service Routine and if the I2C bus is free,

the user can resume communication by asserting a Start

condition.

The master will continue to monitor the SDAx and SCLx

pins. If a Stop condition occurs, the SSPxIF bit will be set.

A write to the SSPxBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I2C bus

can be taken when the P bit is set in the SSPxSTAT

cleared.

SCLx

SDAx

SDAx asserted low before rising edge of clock

Write to SSPxCON2,

set PEN

Falling edge of

SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG

9th clock

SCLx brought high after TBRG

Note:

TBRG = one Baud Rate Generator period.

TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

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