PIC12LF1501 datasheet(176/352 Pages) MICROCHIP

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PIC16(L)F1503

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21.5.3

SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit

and

the

SCLx

held

low

(see

Section21.5.6 “Clock Stretching”

for more detail). By

stretching the clock, the master will be unable to assert

another clock pulse until the slave is done preparing

the transmit data.

The transmit data must be loaded into the SSPxBUF

the SCLx pin should be released by setting the CKP bit

of the SSPxCON1 register. The eight data bits are

shifted out on the falling edge of the SCLx input. This

ensures that the SDAx signal is valid during the SCLx

high time.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCLx input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPxCON2

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDAx line was

low (ACK), the next transmit data must be loaded into

the SSPxBUF register. Again, the SCLx pin must be

released by setting bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPxIF bit must be cleared by software and

the SSPxSTAT register is used to determine the status

of the byte. The SSPxIF bit is set on the falling edge of

the ninth clock pulse.

21.5.3.1

Slave Mode Bus Collision

A slave receives a Read request and begins shifting

data out on the SDAx line. If a bus collision is detected

and the SBCDE bit of the SSPxCON3 register is set,

the BCLxIF bit of the PIRx register is set. Once a bus

collision is detected, the slave goes idle and waits to be

addressed again. User software can use the BCLxIF bit

to handle a slave bus collision.

21.5.3.2

7-bit Transmission

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

accomplish

standard

transmission.

Figure 21-18 can be used as a reference to this list.

Master sends a Start condition on SDAx and

SCLx.

S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

Matching address with R/W bit set is received by

the slave setting SSPxIF bit.

Slave hardware generates an ACK and sets

SSPxIF.

SSPxIF bit is cleared by user.

Software reads the received address from

SSPxBUF, clearing BF.

R/W is set so CKP was automatically cleared

after the ACK.

The slave software loads the transmit data into

SSPxBUF.

CKP bit is set releasing SCLx, allowing the mas-

ter to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

13. Steps 9-13 are repeated for each transmitted

byte.

14. If the master sends a not ACK; the clock is not

held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

Note 1:

If the master ACKs the clock will be

stretched.

ACKSTAT is the only bit updated on the

rising edge of SCLx (ninth) rather than the

falling.

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