LAN9252VSLASHML datasheet(298/329 Pages) MICROCHIP

No. de pieza	LAN9252V/ML

Descripción Electrónicos	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

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Fabricante Electrónico	MICROCHIP [Microchip Technology]

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298 / 329 page

LAN9252

DS00001909A-page 298

 2015 Microchip Technology Inc.

15.3.1

GENERAL PURPOSE TIMER CONFIGURATION REGISTER (GPT_CFG)

This read/write register configures the device’s General Purpose Timer (GPT). The GPT can be configured to generate

host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the General

Purpose Timer Count Register (GPT_CNT). Refer to Section 15.1, "General Purpose Timer," on page 297 for additional

information.

Offset:

08Ch

Size:

32 bits

Bits

Description

Type

Default

31:30

RESERVED

General Purpose Timer Enable (TIMER_EN)

This bit enables the GPT. When set, the GPT enters the run state. When

cleared, the GPT is halted. On the 1 to 0 transition of this bit, the GPT_LOAD

field of this register will be preset to FFFFh.

0: GPT Disabled

1: GPT Enabled

R/W

28:16

RESERVED

15:0

General Purpose Timer Pre-Load (GPT_LOAD)

This value is pre-loaded into the GPT. This is the starting value of the GPT.

The timer will begin decrementing from this value when enabled.

R/W

FFFFh

LAN9252V/ML Datasheet(PDF) 298 Page - Microchip Technology