TMP93CS41 datasheet(115/248 Pages) TOSHIBA

115 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-113

Table 3.7.2 PWM Cycle

at fc

= 20 MHz, fs = 32.768 kHz

PWM Cycle

− 1

Select System

Clock

<SYSCK>

Select

Prescaler Clock

<PRCK1:0>

Gear Value

<GEAR2:0>

φT1

φT4

φT16

φT1

φT4

φT16

φT1

φT4

φT16

1 (fs)

XXX

15.4 ms

61.5 ms

246 ms

31.0 ms

124 ms

496 ms

62.3 ms

249 ms

996 ms

000 (fc)

25.2

µs

100.8

µs403.2 µs 50.8 µs

203.2

µs812.8 µs102.0 µs 408.0 µs 1.63 ms

001 (fc/2)

50.4 µs

201.6 µs806.4 µs101.6 µs406.4 µs

1.63 ms

204.0 µs

816.0 µs

3.26 ms

010 (fc/4)

100.8 µs403.2 µs

1.61 ms

203.2 µs812.8 µs

3.26 ms

408.0 µs

1.63 ms

6.53 ms

011 (fc/8)

201.6

µs806.4 µs 3.23 ms

406.4

µs 1.63 ms

6.52 ms

816.0

µs 3.26 ms

13.06 ms

0 (fc)

(fFPH)

100 (fc/16)

403.2 µs

1.61 ms

6.45 ms

812.8 µs

3.25 ms

13.04 ms 1.63 ms

6.53 ms

26.11 ms

XXX

(Low-frequency

clock)

XXX

15.4 ms

61.5 ms

246 ms

31.0 ms

124 ms

496 ms

62.3 ms

249 ms

996 ms

XXX

(fc/16 clock)

XXX

403.2 µs

1.61 ms

6.45 ms

812.8 µs

3.25 ms

13.04 ms 1.63 ms

6.53 ms

26.11 ms

XXX: Don’t care

(5) The list of 8-bit timer modes

Table 3.7.3 shows the list of 8-bit timer modes.

Table 3.7.3 Timer Mode Setting Registers

TMOD

TFFCR

Bit Name

T10M

PWMM

T1CLK

T0CLK

TFF1IS

Function

Timer Mode

PWM Cycle

Upper Timer

Input Clock

Lower Timer

Input Clock

Timer F/F Invert

Signal Select

16-bit timer mode

−

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

−

8-bit timer

× 2 channels

−

Lower timer match:

φT1, 16, 256

(00, 01, 10, 11)

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

0: Lower timer

output

1: Upper timer

output

8-bit PPG

× 1 channel

−

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

−

8-bit PWM

× 1 channel

− 1, 27 − 1, 28 − 1

(01, 10, 11)

−

External clock,

φT1, φT4, φT16

(00, 01, 10, 11)

−

8-bit timer

× 1 channel

−

φT1, φT16, φT256

(01, 10, 11)

−

Output disabled

−: Don’t care

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