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MPC8280 Datasheet(PDF) 1337 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1337 Page - Freescale Semiconductor, Inc |
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1337 / 1386 page  Parallel I/O Ports MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-21 4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be generated to the core. 5. The pin value can be read at any time using PDATC. NOTE After connecting CTS or CD to the SCC/FCC, the user must also choose the normal operation mode in GSMR[DIAG] to enable and disable SCC/FCC transmission and reception with these pins. The IDMA-DREQ signals on port C can assert an external request to the CP instead of asserting an interrupt to the core. Each line can be programmed to assert an interrupt request upon a high-to-low change or any change as configured in SIEXR. NOTE Do not program the IDMAx-DREQ pins to assert external requests to the IDMA, unless the IDMA is used. Otherwise, erratic operation occurs. |
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