MPC8280 datasheet(1224/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

35-8

Freescale Semiconductor

35.4.1.2

Cell Delineation State Machine Registers 1–8 (CDSMR

The cell delineation state machine register (CDSMRx), as shown in Figure 35-6, holds the ALPHA and

DELTA parameters of the cell delineation state machine.

URE

Underrun interrupt (TCER[UR]) enable. Underrun interrupt may be set when Idle cell is

generated by the TC.

0 Underrun interrupt disabled.

1 Underrun interrupt enabled.

10–11

Loopback/echo modes

00 Normal operation.

01 Cell echo mode operation. Received cells are transmitted and do not go out to the UTOPIA

bus.

10 Data loopback mode operation. Transmit data stream is connected to the receive data

stream.

11 Not used.

Note that for echo mode operation, TCMODE[SM] should be cleared, independent of the FCC

multi-PHY mode configuration.

TBA

Tx Byte align

0 Tx data is transferred as soon as it is enabled.

1 Tx data is transferred byte aligned to the Txsyn signal.

IMA

IMA mode

0 Rx is not in IMA.

1 Rx is in IMA mode.

Single mode

0 TC is not the only PHY on UTOPIA

1 TC is the only PHY on UTOPIA

Cell counters mode

0 Reading a cell counter clears the counter.

1 Reading a cell counter does not change the counter’s value.

Field

ALPHA

DELTA

—

Reset

0000_0000_0000_0000

R/W

Figure 35-6. Cell Delineation State Machine Registers (CDSMR

Table 35-2. TCMODE

x Field Descriptions (continued)

Bits

Name

Description

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