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MPC8280 Datasheet(PDF) 478 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 478 Page - Freescale Semiconductor, Inc |
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478 / 1386 page ![]() Memory Controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 11-58 Freescale Semiconductor Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) Figure 11-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) 11.5.1.4 Output Enable (OE) Timing The timing of the OE is affected only by TRLX. It always asserts and negates on the rising edge of the external bus clock. OE always asserts on the rising clock edge after CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS) by programming TRLX = 1. OE deasserts on the rising clock edge coinciding with or immediately after CS deassertion. Clock Address PSDVAL CS BCTL x WE OE Data ACS = 10 CSNT = 1 Clock Address PSDVAL CS BCTL x WE OE Data |
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