MPC8280 datasheet(462/1386 Pages) FREESCALE

462 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-42

Freescale Semiconductor

11.4.6.6

Refresh Recovery Interval (RFRC)

As represented in Figure 11-25, this parameter, controlled by P/LSDMR[RFRC], defines the earliest

timing for an ACTIVATE command after a REFRESH command.

Figure 11-25. RFRC = 4 (6 Clock Cycles)

11.4.6.7

External Address Multiplexing Signal

In 60x-compatible mode, external address multiplexing is placed on the address lines. If the additional

delay of multiplexing endangers the device setup time, P/LSDMR[EAMUX] should be set. Setting this bit

causes the memory controller to add another cycle for each address phase. Figure 11-26 demonstrates the

timing when EAMUX equals 1.

Note that EAMUX can also be set in any case of delays on the address lines, such as address buffers.

Figure 11-26. EAMUX = 1

11.4.6.8

External Address and Command Buffers (BUFCMD)

In 60x-compatible mode, external buffers may be placed on the command strobes, except CS, as well as

the address lines. If the additional delay of the buffers is endangering the device setup time,

CLK

ALE

SDRAS

SDCAS

MA[0–11]

DQM

A8 = 1

RFRC = 4 (6 clocks)

RAx

PRETOACT

= 3

Precharge

if needed

Auto refresh

Activate command

Bank A

CLK

SDAMUX

CMD

MA[0–11]

Row

Column

NOP

Act

Read

NOP

Address setup cycle

ALE

MPC8280 Datasheet(PDF) 462 Page - Freescale Semiconductor, Inc

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