MPC8280 datasheet(401/1386 Pages) FREESCALE

401 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-93

Table 9-68 describes DMACDARx fields.

9.13.1.6.4

DMA Source Address Registers 0–3 (DMASAR

The source address register, shown in Figure 9-85, indicates the address where the DMA controller will be

reading data from. This address can be in either PCI memory or 60x memory. The software has to ensure

that this is a valid memory address.

The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI

outbound windows, then the source data is read from the PCI memory. Otherwise, it is read from the 60x

memory. Refer to Figure 9-13.

Figure 9-85. DMA Source Address Registers 0–3 (DMASAR

Table 9-69 describes DMASARx fields.

Table 9-68. DMACDAR

x Field Descriptions

Bits

Name

Description

31–5

CDA

Current descriptor address. Contains the current descriptor address of the segment

descriptor in memory. It must be aligned on an 8-word boundary.

SNEN

Snoop enable. When set will allow snooping on DMA transactions.

EOSIE

End-of-segment interrupt enable. When set will generate an interrupt if the current DMA

transfer for the current descriptor is finished.

2–0

—

Reserved, should be cleared.

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x10512(DMASAR0); 0x10592 (DMASAR1); 0x10612 (DMASAR2); 0x10692 (DMASAR3)

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x10510 (DMASAR0); 0x10590 (DMASAR1); 0x10610 (DMASAR2); 0x10690 (DMASAR3)

Table 9-69. DMASAR

x Field Descriptions

Bit

Name

Description

31–0

Source address of DMA transfer. The content is updated after every DMA read operation.

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