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AL1101 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

No. de pieza AL1101
Descripción Electrónicos  24-Bit Analog-to-Digital Converter
Download  8 Pages
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Fabricante Electrónico  ETC2 [List of Unclassifed Manufacturers]
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AL1101 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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6
Digital High Pass Output Filter
The AL1101 has an internal 2.5Hz single pole digital filter, which removes any offset present in
the internal amplifiers and prevents DC codes from appearing at the data outputs. The response
of the filter is -0.067dB at 20Hz.
Clock Generator and PLL
The AL1101 contains an internal PLL that locks to the rising edge of WDCLK and produces all
necessary high frequency clocks and timing signals to operate the device. This high quality PLL
will reject any high-frequency jitter on the incoming wordclock (jitter rejection corner at
approximately 4kHz).
The PLL allows a simplified user interface and eliminates the need of running high frequency
clocks to the part on PCB traces. This reduces unwanted RF noise and coupling problems that
can occur when such clock signals are required on input pins for a device.
Reference and MID
The differential potential between the REF+ and REF- pins (connected to +5V and GND
respectively) determines the amount of charge that is added to or removed from the modulator’s
first stage during each input sample period (64*Fs).
It is very important that REF+ is well
bypassed to REF- (0.1
µF ceramic capacitor as close as possible to the pins) to remove the
unwanted effects of high frequency noise.
The MID potential is developed on-chip (VA/2 Volts) and is used to bias the internal amplifiers in
the modulator, and to provide the reference point which determines the polarity of the modulator
output. It requires a 0.1
µF bypass capacitor to GND at the pin. No load current should be
taken from the MID pin.
Power Supplies and Ground
A single low-impedance +5V supply is all that is required to achieve the specified performance.
A +5V supply plane on the PCB is recommended if possible.
VA and VD may be directly
connected to +5V, and REF+ should be isolated with a 1k
Ω resistor to +5V.
A single low impedance ground plane can be used for all GND connections, simplifying PCB
layout. Each supply pin should be bypassed to GND with a 0.1
µF ceramic capacitor positioned
as close to the pins as possible.


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