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5
Serial Output Interface
The AL1101 presents its two’s complement serial output data in a standard MSB-first format.
Two bitrates are provided: The 32-bits-per-frame rate (FORMAT low) is suitable for use in
systems where 256*Fs master clocks are present. The 24-bits-per-frame rate (FORMAT high) is
convenient when interfacing with circuits where 384*Fs master clocks are present.
The output sample period is defined between rising edges of wordclock (WDCLK) input.
Nominally, this is a 50% duty-cycle clock at frequency Fs, but it can be a pulse with
Ts/256 < Pulse Width < (255/256)*Ts;
Ts=1/Fs.
Left channel data output starts when WDCLK rises, and right channel data output starts Ts/2
seconds later (on falling edge of WDCLK if WDCLK has a 50% duty cycle).
The serial bits are output on the rising edge of an internally generated bitclock (whose rising
edge is aligned with rising edge of WDCLK) that runs at 64*Fs when FORMAT is low (32-bits-per-
frame), or 48*Fs when FORMAT is high (24-bits-per-frame). The data is valid
±100ns from the
center of these bit-frames.
Serial Output Interface Formats
DOUT, 24 bits/frame
DOUT, 32 bits/frame
WDCLK (Fs, 50% duty cycle shown)
Left Channel
Right Channel
23
23
0
0
23
23
0
0
Serial Output Interface Timing
100ns100ns
Ts/48
Ts/96
100ns100ns
Ts/48
100ns
Ts/96
100ns
100ns
100ns
48Fs bitclk (internal)
DOUT
Ts/64
100ns
VALID
64Fs bitclk (internal)
DOUT
Ts/128
100ns
Ts/128
Ts/64
100ns
100ns
100ns
100ns
100ns
100ns
WDCLK (Fs, 50% duty cycle shown)
LEFT
RIGHT
LEFT
RIGHT
VALID
VALID
VALID
VALID
VALID
VALID
VALID
WDCLK (Fs, 50% duty cycle shown)
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