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2
Table of Contents
General Description ………….……………………………….............………….. 1
Features …………………………………………………………..…………….......... 1
Applications ……………………………………….........................……………... 1
Architecture Block Diagram and Package …..………………………………. 1
Table of Contents ………………..……………………………………….............. 2
Pin Descriptions …………………………………………………………………….. 2
Electrical Characteristics ………………………………............…...……….… 3
Recommended Operating Conditions ……..…………….……………... 3
Analog Characteristics …….............………………………………........ 3
Digital Filter Characteristics ...........………………………………........ 3
Digital Inputs ……………………….............……..….......................... 3
Output ……………………………….............……..….......................... 3
Architecture Details …..........…………………………………………………….. 4
Differential Analog Inputs .……............…..……………………...……. 4
Single Ended Input Conditioning Circuit ……...........……… 4
Unbalanced Input Conditioning Circuit ……...........………. 4
Serial Output Interface …….............………………………………....... 5
Serial Output Interface Formats ……………............…………5
Serial Output Interface Timing ……………............……..……5
Digital Highpass Output Filter …..…………............…..…………...... 6
Clock Generator and PLL ……………………............…..…………...... 6
Reference and MID ……………………............…..……..........……...... 6
Power Supplies and Ground ……………………............…..………..... 6
Suggested Connections ………………………………………….………………… 7
Package Dimensions ………………………………………….………………….....7
Notice and Contact Information ………………………………………………...8
Pin Descriptions
Pin#
Name
Pin Type
Description
1
INL+
In
Positive analog input, left channel.
2
INL-
In
Negative analog input, left channel.
3
AGND
Ground
Analog ground.
4
REF+
Power
Positive reference, connect to VDD thru 1k
Ω resistor,
connect 0.1
µF bypass capacitor to REF-.
5
REF-
Ground
Negative reference, connect to GND
6
VD
Power
Digital supply, connect 0.1
µF bypass capacitor to GND.
7
DGND
Ground
Digital ground
8
FORMAT
In
Format select: 0=32 bits/frame, 1=24bits/frame.
9
WDCLK
In
Sample frequency wordclock, 24kHz<Fs<55kHz.
10
DOUT
Out
Serial data output.
11
DGND
Ground
Digital ground.
12
AGND
Ground
Analog ground.
13
VA
Power
Analog supply, connect 0.1
µF bypass capacitor to GND.
14
MID
I/O
Mid reference, connect 0.1
µF bypass capacitor to GND.
15
INR-
In
Negative analog input, right channel.
16
INR+
In
Positive analog input, right channel.
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