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ST7LITE49M Datasheet(PDF) 112 Page - STMicroelectronics |
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ST7LITE49M Datasheet(HTML) 112 Page - STMicroelectronics |
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112 / 188 page ![]() On-chip peripherals ST7LITE49M 112/188 Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 55. Figure 55. I2C bus protocol Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast I2C (up to 400KHz). SDA/SCL line control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data register. The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. SCL SDA 12 8 9 MSB ACK STOP START CONDITION CONDITION VR02119B |
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