ST92F124 datasheet(425/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

Figure 8. Impact of negative current injection on adjacent pin

Impact on application

If the adjacent I/O is used as an analog input (Port

7 and 8 only), the current drawn through the ex-

ternal resistor generates a difference in potential,

resulting in a conversion error.

13.8.5 I2CECCR REGISTER LIMITATION

It is not possible to write to the CC7 and CC8 bits

in the I2CECCR register. These bits remain at

their reset value (0).

Impact on application

The baudrate prescaler cannot be higher than 258

(CC8:7=0 and CC6:0=1). As a consequence, the

baudrate cannot be lower than fSCL=INTCLK/258

Workaround

None.

13.8.6 I2C BEHAVIOUR DISTURBED DURING

DMA TRANSACTIONS

Description

If a DMA transfer occurs on SCI-M, MFT or J1850

during I2C transmission or reception, I2C periph-

eral may be disturbed.

In transmission mode, additional bytes can be ob-

served on I2C lines (SDA and SCL). In reception

mode, additional bytes can be seen in the I2CDR

Workaround

Avoid using DMA transfer while I2C peripheral is

running.

13.8.7 MFT DMA MASK BIT RESET

The limitation described in Section 13.7 on page

419 applies whatever the MFT0 DMA priority level.

13.8.8 DMA DATA CORRUPTED BY MFT INPUT

CAPTURE

Description

If the MFT requests a DMA transfer following an

input capture event and while a DMA transfer is

currently ongoing to or from another peripheral

(SCI-M, I2C, or second MFT), the DMA data is cor-

rupted (overwritten by the captured data).

Workaround

Avoid using the MFT Input Capture function in

DMA mode while another peripheral is in DMA

mode.

100

150

200

250

300

350

Current injection (mA)

Current drawn

from adjacent

pin (uA,

absolute

value)

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