ST92F124 datasheet(419/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

13.7 MFT DMA MASK BIT RESET WHEN MFT0

DMA PRIORITY LEVEL IS SET TO 0

Introduction

The MultiFunction Timer is a 16-bit timer with Input

Capture and Output Compare modes. In Input

Capture mode, the timer value is saved when an

external event occurs. In Output Compare mode,

the timer changes an I/O pin level when it reaches

the Compare Register value.

In these two modes the event (Input Capture or

Output Compare) may generate an interrupt or re-

quest a Direct Memory Access.

– In interrupt Input Capture mode (or Output Com-

pare mode), the interrupt routine saves the coun-

ter in the RAM or the Register File (or updates

the compare register from a location in RAM or

in the Register File).

– In DMA mode these transfers are done automat-

ically.

The choice between Interrupt or DMA modes is

defined by the CP0D and CM0D bits (bit 6 and bit

3 in the IDMR register, R255 page 10/8).

CP0D : Capture 0 DMA Mask. Capture on REG0R

DMA is enabled when CP0D = 1.

CM0D: Compare 0 DMA Mask. Compare on

CMP0R DMA is enabled when CM0D = 1.

In DMA mode a DMA counter register and a DMA

address register define the location and the size of

the memory block (RAM or Reg. File) involved in

these transfers.

Each DMA transfer decreases the counter value.

When the counter reaches 0, an EndOfBlock

event occurs on the DMA controller. This event is

detected by the MFT which resets the CP0D or the

CM0D bit.

Limitation Description

The MFT1 resets its DMA Mask bit even if the

End-of-Block signal is dedicated to the MFT0.

This limitation occurs if the following conditions are

fulfilled:

– a MFT DMA request (for instance MFT1) occurs

while another peripheral DMA request is being

serviced (for instance MFT0),

– the MFT0 DMA request corresponds to an End-

of-Block

– the MFT0 DMA priority level is set to 0.

This limitation is due to wrong End-of-Block event

management by the MFT, it does not impact the

SCI and the I2C but they can be involved in the

limitation if:

– First peripheral requests a DMA transfer with

End-of-Block event,

– Other peripherals request a DMA transfer with a

higher priority level between the same two DMA

arbitrations. As a consequence, the MFT1 DMA

request is not serviced and a DMA transfer is

lost. This is also true for a Top Level Interrupt

(higher priority than DMA).

ST92F124 Datasheet(PDF) 419 Page - STMicroelectronics

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