ST92F124 datasheet(414/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING

Description

Under certain conditions, FIFO corruption can

occur in the following cases:

WHEN a bxCAN RX FIFO already holds 2 mes-

sages (i.e. FMP==2)

AND the application releases the same FIFO

(with the instruction CANx_CTRL_CRFRy |=

CRF_rfom;

x=0 for the CAN_0 cell

x=1 for the CAN_1 cell

y=0 for the Receive FIFO 0

y=1 for the Receive FIFO 1 )

WHILE the bxCAN requests the transfer of a new

receive message into the FIFO (this lasts one CPU

cycle)

THEN the internal FIFO pointer is not updated

BUT the FMP bits are updated correctly

Impact on Application:

As the FIFO pointer is not updated correctly, this

causes the last message received to be over-

written by any incoming message. This means one

message is lost as shown in the example in Figure

2 The bxCAN will not recover normal operation

until a device reset occurs.

Figure 2. FIFO Corruption

Initial State

* pointer to next receive location

v pointer to next message to be released

-- -

When the FIFO is empty, v and * point to the same location

FIFO

Receive Message A

A- -

Receive Message B

AB-

Receive Message C

ABC

* does not move because FIFO is full (normal operation)

Release Message A

ABC

Release Message B

DB C

and Receive Message D

DB C

Normal operation

* Does not move, pointer curruption

Receive Message E

EB C

Release Message C

EBC

Release Message E

EBC

C released

* v

Release Message B

EBC

* v

* and v are not pointing to the same message

D is overwritten by E

FMP

the FIFO is empty

E released instead of B

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