ST92F124 datasheet(345/429 Pages) STMICROELECTRONICS

345 / 429 page

345/429

CONTROLLER AREA NETWORK (bxCAN)

CONTROLLER AREA NETWORK (Cont’d)

Bit 4 = TXOK0 Transmission OK for mailbox 0

- Read

This bit is set by hardware when the transmission

request on mailbox 0 has been completed suc-

cessfully. Please refer to Figure 147.

This bit is cleared by hardware when mailbox 0 is

requested for transmission or when the software

clears the RQCP0 bit.

Bit 3 = Reserved. Forced to 0 by hardware.

Bit 2 = RQCP2 Request Completed for Mailbox 2

- Read/Clear

This bit is set by hardware to signal that the last re-

quest for mailbox 2 has been completed. The re-

quest could be a transmit or an abort request.

This bit is cleared by software.

Bit 1 = RQCP1 Request Completed for Mailbox 1

- Read/Clear

This bit is set by hardware to signal that the last re-

quest for mailbox 1 has been completed. The re-

quest could be a transmit or an abort request.

This bit is cleared by software.

Bit 0 = RQCP0 Request Completed for Mailbox 0

- Read/Clear

This bit is set by hardware to signal that the last re-

quest for mailbox 0 has been completed. The re-

quest could be a transmit or an abort request.

This bit is cleared by software.

CAN TRANSMIT PRIORITY REGISTER (CTPR)

All bits of this register are read only.

Reset Value: 0000 0000 (00h)

Bit 7 = LOW2 Lowest Priority Flag for Mailbox 2

- Read

This bit is set by hardware when more than one

mailbox are pending for transmission and mailbox

2 has the lowest priority.

Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1

- Read

This bit is set by hardware when more than one

mailbox are pending for transmission and mailbox

1 has the lowest priority.

Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0

- Read

This bit is set by hardware when more than one

mailbox are pending for transmission and mailbox

0 has the lowest priority.

Note: These bits are set to zero when only one

mailbox is pending.

Bit 4 = TME2 Transmit Mailbox 2 Empty

- Read

This bit is set by hardware when no transmit re-

quest is pending for mailbox 2.

Bit 3 = TME1 Transmit Mailbox 1 Empty

- Read

This bit is set by hardware when no transmit re-

quest is pending for mailbox 1.

Bit 2 = TME0 Transmit Mailbox 0 Empty

- Read

This bit is set by hardware when no transmit re-

quest is pending for mailbox 0.

Bit 1:0 = CODE[1:0] Mailbox Code

- Read

In case at least one transmit mailbox is free, the

code value is equal to the number of the next

transmit mailbox free.

In case all transmit mailboxes are pending, the

code value is equal to the number of the transmit

mailbox with the lowest priority.

LOW2

LOW1

LOW0

TME2

TME1

TME0

CODE1

CODE0

ST92F124 Datasheet(PDF) 345 Page - STMicroelectronics

ST92F124 Datasheet(HTML) 345 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL