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AT83SND1CXXX-ROTIL Datasheet(PDF) 176 Page - ATMEL Corporation

No. de pieza AT83SND1CXXX-ROTIL
Descripción Electrónicos  Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
PDF  212 Pages
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Fabricante Electrónico  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT83SND1CXXX-ROTIL Datasheet(HTML) 176 Page - ATMEL Corporation

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4109J–8051–10/06
AT8xC51SND1C
enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by
software.
20.2
Registers
Table 137. ADCON Register
ADCON (S:F3h) – ADC Control Register
Reset Value = 0000 0000b
Table 138. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
Reset Value = 0000 0000b
7654
3210
-
ADIDL
ADEN
ADEOC
ADSST
-
-
ADCS
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
The value read from this bit is always 0. Do not set this bit.
6
ADIDL
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
5ADEN
ADC Enable Bit
Set to enable the A to D converter.
Clear to disable the A to D converter and put it in low power stand by mode.
4ADEOC
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
3ADSST
Start and Status Bit
Set to start an A to D conversion on the selected channel.
Cleared by hardware at the end of conversion.
2 - 1
-
Reserved
The value read from these bits is always 0. Do not set these bits.
0ADCS
Channel Selection Bit
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
7654
3210
-
-
-
ADCD4
ADCD3
ADCD2
ADCD1
ADCD0
Bit
Number
Bit
Mnemonic
Description
7 - 5
-
Reserved
The value read from these bits is always 0. Do not set these bits.
4 - 0
ADCD4:0
ADC Clock Divider
5-bit divider for ADC clock generation.



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