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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AT83SND1CXXX-ROTIL Datasheet(PDF) 152 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Datasheet(HTML) 152 Page - ATMEL Corporation |
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152 / 212 page  152 4109J–8051–10/06 AT8xC51SND1C Figure 18-9. Master SPI Polling Flows 18.3.5 Master Mode with Interrupt Figure 18-10 shows the initialization phase and the transfer phase flows using the interrupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 121. The transfer format depends on the slave peripheral. SS may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. SPI Initialization Polling Policy Disable interrupt SPIE = 0 SPI Transfer Polling Policy End Of Transfer? SPIF = 1? Select Master Mode MSTR = 1 Select Bit Rate program SPR2:0 Select Format program CPOL & CPHA Enable SPI SPEN = 1 Select Slave Pn.x = L Start Transfer write data in SPDAT Last Transfer? Get Data Received read SPDAT Deselect Slave Pn.x = H |
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