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AT83SND1CXXX-ROTIL Datasheet(PDF) 141 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Datasheet(HTML) 141 Page - ATMEL Corporation |
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141 / 212 page  141 4109J–8051–10/06 AT8xC51SND1C 17.6.2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR = 0101 0110b SADEN = 1111 1100b (SADDR | SADEN)=1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 1X11b, Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 1X11b, Slave C:SADDR = 1111 0010b SADEN = 1111 1101b Given = 1111 1111b, For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send the address FFh. To communicate with slaves A and B, but not slave C, the master must send the address FBh. 17.6.3 Reset Address On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the Serial Port is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 17.7 Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 17-16 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by soft- ware when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are glo- bally enabled by setting EA bit in IEN0 register. Depending on the selected mode and weather the framing error detection is enabled or dis- abled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 17-17. |
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