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ST7L19 Datasheet(PDF) 121 Page - STMicroelectronics |
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ST7L19 Datasheet(HTML) 121 Page - STMicroelectronics |
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121 / 138 page ![]() ST7L15, ST7L19 121/138 COMMUNICATION INTERFACE CHARACTERISTICS (cont’d) Figure 97. SPI Slave Timing Diagram with CPHA = 11) Figure 98. SPI Master Timing Diagram1) Notes: 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. When no communication is on-going, the alternate function capability of the SPI’s data output line (MOSI in master mode, MISO in slave mode) is released. In this case, the pin status depends on the I/O port configuration. SS INPUT CPHA = 1 MOSI INPUT MISO OUTPUT CPHA = 1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT See CPOL = 0 CPOL = 1 tsu(SS) th(SS) tdis(SO) th(SO) See note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN SS INPUT CPHA = 0 MOSI OUTPUT MISO INPUT CPHA = 0 CPHA = 1 CPHA = 1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN Seenote2 Seenote2 CPOL = 0 CPOL = 1 CPOL = 0 CPOL = 1 tr(SCK) tf(SCK) th(MO) tv(MO) |
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