UPD17708 datasheet(318/358 Pages) RENESAS

No. de pieza	UPD17708

Descripción Electrónicos	MOS INTEGRATED CIRCUIT

PDF	358 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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318 / 358 page

316

µPD17704, 17705, 17707, 17708, 17709

21.4 Relationship between CE Reset and Power-ON Reset

On the first application of supply voltage VDD, power-ON reset and CE reset are performed at the same time.

The reset operations at this time are described in 21.4.1 through 21.4.3.

21.4.4 describes the points to be noted when raising supply voltage VDD.

21.4.1 If VDD pin and CE pin go high at the same time

Figure 21-7 (a) shows the operation.

At this time, the program starts from address 0000H because of power-ON reset.

21.4.2 If CE pin rises in forced halt status set by power-ON reset

Figure 21-7 (b) shows the operation.

At this time, the program starts from address 0000H because of power-ON reset, in the same manner as 21.4.1.

21.4.3 If CE pin rises after power-ON reset

Figure 21-7 (c) shows the operation.

At this time, the program starts from address 0000H because of power-ON reset, and the program starts from

address 0000H again at the rising edge of the next basic timer 0 carry FF setting signal because of CE reset.

UPD17708 Datasheet(PDF) 318 Page - Renesas Technology Corp