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CYT4DNJBJS Datasheet(PDF) 136 Page - Infineon Technologies AG |
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CYT4DNJBJS Datasheet(HTML) 136 Page - Infineon Technologies AG |
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136 / 209 page  Datasheet 136 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications Figure 26-10 SPI master timing diagrams with LOW clock phase SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1) CPHA=0 SSEL SCLK (CPOL=0) SCLK (CPOL=1) MISO (input) MOSI (output) 2 5 6 4 4 1 7 3 8 9 1: SCLK period = 1 / fSPI 2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM) 3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM) 4: SCLK high or low time = tW_SCLK_H_L 5: Input data setup time = tDSI 6: Input data hold time = tDHI 7: Output data valid after SCLK driving edge = tDMO 8: Output data hold time = tHMO 9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM) |
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