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STM32U545NET3QTR Datasheet(PDF) 230 Page - STMicroelectronics |
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STM32U545NET3QTR Datasheet(HTML) 230 Page - STMicroelectronics |
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230 / 283 page ![]() Electrical characteristics STM32U545xx 230/283 DS14216 Rev 1 PSRR DC VDDA supply rejection ratio Normal mode DAC output buffer ON CL ≤ 50 pF, RL = 5 kΩ --80 -28 dB tSAMP Sampling time in sample and hold mode, CSH = 100 nF (code transition between the lowest input code and the highest input code when DACOUT reaches the final value ±1 LSB) DAC_OUT pin connected DAC output buffer ON, CSH = 100 nF -0.7 1.9 ms DAC output buffer OFF, CSH = 100 nF -10.5 15 DAC_OUT pin not connected (internal connection only) DAC output buffer OFF -2 8 µs Ileak Output leakage current - - - (3) nA CIint Internal sample and hold capacitor -7 9.2 11 pF tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs Voffset Middle code offset for 1 trim code step VREF+ = 3.6 V - 1520 - µV VREF+ = 1.6 V - 680 - IDDA(DAC) DAC consumption from VDDA DAC output buffer ON No load, middle code (0x800) - 330 510 µA No load, worst code (0xF1C) - 470 680 DAC output buffer OFF No load, middle/worst code (0x800) -- 0.3 Sample and hold mode, CSH = 100 nF - 330 × TON /(TON + TOFF) (4) 680 × TON /(TON + TOFF) (4) Table 113. DAC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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