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STM32U535NET6QTR Datasheet(PDF) 240 Page - STMicroelectronics

No. de pieza STM32U535NET6QTR
Descripción Electrónicos  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, up to 512 KB flash memory, 274 KB SRAM
PDF  278 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U535NET6QTR Datasheet(HTML) 240 Page - STMicroelectronics

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Electrical characteristics
STM32U535xx
240/278
DS14217 Rev 1
5.3.30
PSSI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 32, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
PSSI_PDCK polarity: falling
•
PSSI_RDY and PSSI_DE polarity: low
•
Bus width: 16 lines
•
Data width: 32 bits
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Table 119. PSSI transmit characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
Frequency ratio DCMI_PDCK/fHCLK
--
0.4
-
PSSI_PDCK PSSI clock input
2.7 V ≤ VDD ≤ 3.6 V
-
64(2)
MHz
1.71 V ≤ VDD ≤ 3.6 V
-
47(2)
DPIXEL
PSSI clock input duty cycle
-
30
70
%
tOV(DATA)
Data output valid time
2.7 V ≤ VDD ≤ 3.6 V
-
14
ns
1.71 V ≤ VDD ≤ 3.6 V
-
21
tOH(DATA)
Data output hold time
1.71 V ≤ VDD ≤ 3.6 V
7-
tOV(DE)
DE output valid time
-
12.5
tOH(DE)
DE output hold time
6
-
tSU(RDY)
RDY input setup time
1.71 V ≤ VDD ≤ 3.6 V
0-
tH(RDY)
RDY input hold time
0
-
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.



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