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KSZ9563RNXC-TR Datasheet(PDF) 165 Page - Microchip Technology |
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KSZ9563RNXC-TR Datasheet(HTML) 165 Page - Microchip Technology |
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165 / 226 page ![]() 2017-2018 Microchip Technology Inc. DS00002419D-page 165 KSZ9563R 5.2.6.18 Port ACL Byte Enable LSB Register 5.2.6.19 Port ACL Access Control 0 Register Address: 0xN611 Port N: 1-3 Size: 8 bits Bits Description Type Default 7:0 Byte Enable [7:0] Each bit enables accessing one of the ACL bytes when a read or write is initiated by writing to the Port ACL Byte Enable LSB Register. Bit 0 applies to the Port ACL Access F Register Bit 1 applies to the Port ACL Access E Register, etc. Bit 7 applies to the Port ACL Access 8 Register 1 = Byte is selected for read/write 0 = Byte is not selected R/W 0x00 Address: 0xN612 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED R/O 0b 6 Write Status 1 = Write operation is complete 0 = Write operation is not complete RO 1b 5 Read Status 1 = Read operation is complete 0 = Read operation is not complete; continue polling until this bit is set before reading results registers RO 1b 4 Write / Read 1 = Write 0 = Read R/W 0b 3:0 ACL Index R/W 0x0 |
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