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STM32H757AI Datasheet(PDF) 223 Page - STMicroelectronics |
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STM32H757AI Datasheet(HTML) 223 Page - STMicroelectronics |
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223 / 251 page  DS12931 Rev 1 223/251 STM32H757xI Electrical characteristics 230 Figure 62. MDIO Slave timing diagram SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 124 and Table 125 for SDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 0x11 • Capacitive load CL=30 pF • Measurement points are done at CMOS levels: 0.5VDD • IO Compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS1 Refer to Section 6.3.18: I/O port characteristics for more details on the input/output characteristics. MSv40460V1 tsu(MDIO) tMDC) th(MDIO) td(MDIO) Table 124. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 133 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fPP =52MHz 8.5 9.5 - ns tW(CKH) Clock high time fPP =52MHz 8.5 9.5 - CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode tISU Input setup time HS - 1.5 - - ns tIH Input hold time HS - 1.5 - - tIDW(4) Input valid window (variable window) - 3 - - - CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode tOV Output valid time HS - - 3.5 5 ns tOH Output hold time HS - 2 - - |
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