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STM32H757AI Datasheet(PDF) 218 Page - STMicroelectronics

No. de pieza STM32H757AI
Descripción Electrónicos  Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI, crypto
PDF  251 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STM32H757AI Datasheet(HTML) 218 Page - STMicroelectronics

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Electrical characteristics
STM32H757xI
218/251
DS12931 Rev 1
I2S Interface characteristics
Unless otherwise specified, the parameters given in Table 121 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
Table 121. I2S dynamic characteristics(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S main clock output
-
256x8K
256FS
MHz
fCK
I2S clock frequency
Master data
-
64FS
MHz
Slave data
-
64FS
tv(WS)
WS valid time
Master mode
-
3
ns
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
1
-
th(WS)
WS hold time
Slave mode
1
-
tsu(SD_MR)
Data input setup time
Master receiver
1
-
tsu(SD_SR)
Slave receiver
1
-
th(SD_MR)
Data input hold time
Master receiver
4
-
th(SD_SR)
Slave receiver
2
-
tv(SD_ST)
Data output valid time
Slave transmitter (after enable
edge)
-17
tv(SD_MT)
Master transmitter (after
enable edge)
-3
th(SD_ST)
Data output hold time
Slave transmitter (after enable
edge)
9-
th(SD_MT)
Master transmitter (after
enable edge)
0-



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