MPC8540 datasheet(194/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-8

Freescale Semiconductor

Reset, Clocking, and Initialization

4.3.1.3.1

Boot Page Translation Register (BPTR)

Figure 4-4 shows the fields of BPTR.

Figure 4-4. Boot Page Translation Register (BPTR)

Table 4-8 describes BPTR field descriptions.

4.3.2

Boot Sequencer

The boot sequencer is a DMA engine that accesses a serial ROM on the I

2C interface and writes

data to CCSR memory or the memory space pointed to by the alternate configuration base address

sequencer is enabled by reset configuration pins as described in Section 4.4.3.6, “Boot Sequencer

Configuration.” If the boot sequencer is enabled, the e500 core is held in reset until the boot

sequencer has completed its operation. For more details, see Section 11.4.5, “Boot Sequencer

Mode,” in the I

2C chapter.

4.4

Functional Description

This section describes the various ways to reset the MPC8540 device, the POR configurations, and

the clocking on the MPC8540.

4.4.1

Reset Operations

The MPC8540 has reset input signals for hard and soft reset operation.

11 12

0 0000 00 0 0 0 0

BOOT_PAGE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x020

Table 4-8. BPTR Field Descriptions

Bits

Name

Description

Boot page translation enable

0 Boot page is not translated

1 Boot page is translated as defined in the BPTR[BOOT_PAGE] parameter

1–11

—

Write reserved, read = 0

12–31 BOOT_PAGE Translation for boot page. If enabled, the high-order 20 bits of accesses to 0xFFFF_Fnnn are

replaced with this value.

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