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CS47L35 Datasheet(PDF) 241 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 241 Page - Cirrus Logic |
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241 / 300 page  DS1085F3 241 CS47L35 5.4 Digital Audio Interface Clocking Configurations Fig. 5-15 shows AIF Master Mode operation, using a separate interface as the clock reference. In this example, the FLL is used to generate the system clock, with SLIMCLK as the reference. Figure 5-15. AIF Master Mode, Using Another Interface as Reference Fig. 5-16 shows AIF Slave Mode operation, using BCLK as the clock reference. In this example, the FLL is used to generate the system clock, with BCLK as the reference. Figure 5-16. AIF Slave Mode, Using BCLK and FLL as Reference Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SLIMCLK SLIMDAT FRAMER_REF_GEAR Processor Processor AIFn (Master Mode) AIFn (Slave Mode) SLIMbus Interface Automatic Divider MCLK1 MCLK2 SYSCLK SYSCLK_SRC AIFnBCLK SLIMCLK MCLK1 MCLK2 CS47L35 Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 AIFn (Slave Mode) AIFnBCLK MCLK1 MCLK2 SLIMCLK SYSCLK SYSCLK_SRC AIFnBCLK SLIMCLK MCLK1 MCLK2 CS47L35 |
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