CC2430-RTR1-F64Z datasheet(134/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 134 of 232

unrolling is used, so that a new byte can

be written to RNDH every clock cycle.

Note that the LFSR must be properly

seeded by writing to RNDL, before the

CRC calculations start. Usually the seed

value should be 0x0000 or 0xFFFF.

13.8.3 Random Number Generator Registers

This section describes the Random Number Generator registers.

RNDL (0xBC) – Random Number Generator Data Low Byte

Bit

Name

Reset

R/W

Description

[7:0]

RNDL[7:0]

0xFF

R/W

Random value/seed or CRC result, low byte

When used for random number generation writing this register

twice will seed the random number generator. Writing to this

replaces the 8 LSBs with the data value written.

The value returned when reading from this register is the 8 LSBs

of the LSFR.

When used for random number generation, reading this register

returns the 8 LSBs of the random number. When used for CRC

calculations, reading this register returns the 8 LSBs of the CRC

result.

RNDH (0xBD) – Random Number Generator Data High Byte

Bit

Name

Reset

R/W

Description

[7:0]

RNDH[7:0]

0xFF

R/W

Random value or CRC result/input data, high byte

When written, a CRC16 calculation will be triggered, and the data

value written is processed starting with the MSB bit.

The value returned when reading from this register is the 8 MSBs

of the LSFR.

When used for random number generation, reading this register

returns the 8 MSBs of the random number. When used for CRC

calculations, reading this register returns the 8 MSBs of the CRC

result.

CC2430-RTR1-F64Z Datasheet(PDF) 134 Page - Texas Instruments

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