D301 datasheet(344/416 Pages) MICROCHIP

344 / 416 page

PIC24FJ256GA705 FAMILY

DS30010118D-page 344

 2016-2018 Microchip Technology Inc.

29.5

Program Verification and

Code Protection

PIC24FJ256GA705

family

devices

offer

basic

implementation of CodeGuard™ Security that supports

General Segment (GS) security and Boot Segment

(BS) security. This feature helps protect individual

intellectual property.

29.6

JTAG Interface

PIC24FJ256GA705 family devices implement a JTAG

interface, which supports boundary scan device

testing.

29.7

In-Circuit Serial Programming

PIC24FJ256GA705 family microcontrollers can be seri-

ally programmed while in the end application circuit. This

is simply done with two lines for clock (PGCx) and data

(PGDx), and three other lines for power (VDD), ground

(VSS) and MCLR. This allows customers to manufacture

boards with unprogrammed devices and then program

the microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

29.8

Customer OTP Memory

PIC24FJ256GA705 family devices provide 256 bytes of

One-Time-Programmable (OTP) memory, located at

addresses, 801700h through 8017FEh. This memory

can be used for persistent storage of application-specific

information that will not be erased by reprogramming the

device. This includes many types of information, such as

(but not limited to):

• Application checksums

• Code revision information

• Product information

• Serial numbers

• System manufacturing dates

• Manufacturing lot numbers

PIC24FJ256GA705 family devices provide 256 bytes

of One-Time-Programmable (OTP) memory, and this

OTP memory can be written by program execution(i.e.,

TBLWT instructions) and during device programming.

Data is not cleared by a chip erase.

29.9

In-Circuit Debugger

This function allows simple debugging functions when

used with MPLAB® IDE. Debugging functionality is

controlled through the PGCx (Emulation/Debug Clock)

and PGDx (Emulation/Debug Data) pins.

To use the in-circuit debugger function of the device,

the design must implement ICSP™ connections to

MCLR, VDD, VSS and the PGCx/PGDx pin pair, desig-

nated by the ICS<1:0> Configuration bits. In addition,

when the feature is enabled, some of the resources are

not available for general use. These resources include

the first 80 bytes of data RAM and two I/O pins.

Note:

For more information on usage, configura-

tion and operation, refer to the “dsPIC33/

PIC24

Family

Reference

Manual”,

“CodeGuard™ Intermediate Security”

(DS70005182).

Note:

Data in the OTP memory section MUST

NOT be programmed more than once.

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