12 Layout

12.1 Layout Guidelines

12.1.1 Component Placement

Place all the external components close to the TPA2015D1 device. Placing the decoupling capacitors as close

as possible to the device is important for the efficiency of the class-D amplifier. Any resistance or inductance in

the trace between the device and the capacitor can cause a loss in efficiency.

12.1.2 Trace Width

Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB

traces. For high current pins (SW, GND, OUT+, OUT–, PVOUT, and PVDD) of the TPA2015D1, use 100 μm

trace widths at the solder balls and at least 500 μm PCB traces to ensure proper performance and output power

for the device. For low current pins (IN–, IN+, END, ENB, GAIN, AGC, VBAT) of the TPA2015D1, use 75 μm to

100 μm trace widths at the solder balls. Run IN- and IN+ traces side-by-side (and if possible, same length) to

maximize common-mode noise cancellation.

12.1.3 Pad Size

In making the pad size for the DSBGA balls, TI recommends that the layout use nonsolder mask defined

(NSMD) land.

With this method, the solder mask opening is made larger than the desired land area, and the opening size

is defined by the copper pad width. Figure 12-1 and Table 12-1 show the appropriate diameters for a DSBGA

layout.

Copper

Trace Width

Solder

Pad Width

Solder Mask

Opening

Copper Trace

Thickness

Solder Mask

Thickness

Figure 12-1. Land Pattern Dimensions

Table 12-1. Land Pattern Dimensions(1) (3) (2) (4)

SOLDER PAD

DEFINITIONS

COPPER

PAD

SOLDER MASK (5)

OPENING

COPPER

THICKNESS

STENCIL (6) (7)

OPENING

STENCIL

THICKNESS

Nonsolder mask

defined (NSMD)

275 μm

(+0.0, -25 μm)

375 μm (+0.0, -25 μm)

1 oz max (32 μm)

275 μm x 275 μm Sq.

(rounded corners)

125 μm thick

(1)

Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.

Wider trace widths reduce device stand off and impact reliability.

(2)

Recommend solder paste is Type 3 or Type 4.

(3)

Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the

intended application.

(4)

For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.

(5)

Solder mask thickness should be less than 20 μm on top of the copper circuit pattern

(6)

Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in

inferior solder paste volume control.

(7)

Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to

solder wetting forces.

TPA2015D1

SLOS638C – NOVEMBER 2011 – REVISED JUNE 2022

www.ti.com

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