PIC16F616-ESLASHML datasheet(115/172 Pages) APEX

115 / 172 page

Preliminary

DS41288A-page 113

PIC16F616/16HV616

FIGURE 11-9:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

11.8

Code Protection

the

code

protection

bit(s)

have

not

been

programmed, the on-chip program memory can be

read out using ICSP™ for verification purposes.

11.9

ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

TOST(2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes.

GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

Note:

The entire Flash program memory will be

erased when the code protection is turned

off. See the “PIC12F6XX/16F6XX Memory

Programming Specification” (DS41204)

for more information.

PIC16F616-E/ML Datasheet(PDF) 115 Page - Cirrus Logic

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