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STM32F730Z8 Datasheet(PDF) 151 Page - STMicroelectronics

No. de pieza STM32F730Z8
Descripción Electrónicos  Arm® Cortex®-M7 32b MCUFPU, 462DMIPS, 64KB Flash /256164KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
PDF  202 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F730Z8 Datasheet(HTML) 151 Page - STMicroelectronics

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DS12536 Rev 2
151/202
STM32F730x8
Electrical characteristics
185
Figure 44. SPI timing diagram - slave mode and CPHA = 0
tsu(MI)
Data input setup time
Master mode
4
-
-
ns
tsu(SI)
Slave mode
3.5
-
-
th(MI)
Data input hold time
Master mode
3
-
-
th(SI)
Slave mode
1
-
-
ta(SO)
Data output access time
Slave mode
7
9
21
tdis(SO)
Data output disable time
Slave mode
5
7
12
tv(SO)
Data output valid time
Slave mode 2.7≤VDD≤3.6V
-
6.5
10
Slave mode 1.71≤VDD≤3.6V
-
6.5
13.5
tv(MO)
Master mode
-
2
3
th(SO)
Data output hold time
Slave mode
1.71≤VDD≤3.6V
4.5
-
-
th(MO)
Master mode
0
-
-
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.
3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
Table 81. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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