MPC8544EBVTARGA datasheet(114/117 Pages) NXP

114 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

114

Freescale Semiconductor

Device Nomenclature

Option 2

•

If PCI arbiter is disabled during POR,

•

All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied

to OVDD through a single (or multiple) 10-kΩ resistor(s).

•

All PCI control pins can be grouped together and tied to OVDD through a single 10-kΩ resistor.

21.12 Guideline for LBIU Termination

If the LBIU parity pins are not used, the following list shows the termination recommendation:

•

For LDP[0:3]: tie them to ground or the power supply rail via a 4.7-k

Ω resistor.

•

For LPBSE: tie it to the power supply rail via a 4.7-k

Ω resistor (pull-up resistor).

22 Device Nomenclature

Ordering information for the parts fully covered by this hardware specifications document is provided in

Section 22.3, “Part Marking.” Contact your local Freescale sales office or regional marketing team for

order information.

22.1

Industrial and Commercial Tier Qualification

The MPC8544E device has been tested to meet the industrial tier qualification. Table 74 provides a

description for commercial and industrial qualifications.

Table 74. Commercial and Industrial Description

Tier1

Typical Application

Use Time

Power-On Hours

Example of Typical Applications

Commercial

5 years

Part-time/ Full-Time PC's, consumer electronics, office automation, SOHO networking,

portable telecom products, PDAs, etc.

Industrial

10 years

Typically Full-Time

Installed telecom equipment, work stations, servers, warehouse

equipment, etc.

Note:

1. Refer to Table 2 for operating temperature ranges. Temperature is independent of tier and varies per product.

MPC8544EBVTARGA Datasheet(PDF) 114 Page - NXP Semiconductors

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