MPC8544EBVTARGA datasheet(105/117 Pages) NXP

105 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

105

System Design Information

where:

Ifw = Forward current

Is = Saturation current

Vd = Voltage at diode

Vf = Voltage forward biased

VH = Diode voltage while IH is flowing

VL = Diode voltage while IL is flowing

IH = Larger diode bias current

IL = Smaller diode bias current

q = Charge of electron (1.6

× 10 –19 C)

n = Ideality factor (normally 1.0)

K = Boltzman’s constant (1.38

× 10–23 Joules/K)

T = Temperature (Kelvins)

The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following:

VH – VL = 1.986 × 10–4 × nT

Solving for T, the equation becomes:

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8544E.

21.1

System Clocking

This device includes six PLLs:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The

frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio

configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”

•

The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e500 core clock and the platform clock is selected using the e500 PLL ratio

configuration bits as described in Section 19.3, “e500 Core PLL Ratio.”

•

The PCI PLL generates the clocking for the PCI bus.

•

The local bus PLL generates the clock for the local bus.

•

There are two PLLs for the SerDes block.

VH – VL

1.986

× 10–4

nT =

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