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IMX6SDLCEC Datasheet(PDF) 101 Page - NXP Semiconductors |
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IMX6SDLCEC Datasheet(HTML) 101 Page - NXP Semiconductors |
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101 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 101 corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals. Figure 64. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 65 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable. Figure 65. TFT Panels Timing Diagram—Vertical Sync Pulse DI clock VSYNC DRDY D0 D1 IP5o IP13o IP9o IP8o IP8 IP9 Dn IP10 IP7 IP5 IP6 IPP_DISP_ CLK IPP_DATA HSYNC IP14 VSYNC HSYNC DRDY Start of frame End of frame IP12 IP15 IP13 IP11 |
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