AM652X datasheet(177/282 Pages) TI

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QEP_S

QEP4

EPERIPHERALS_TIMNG_03

QEP_I

QEP2

QEP_A/B

QEP1

QEP3

QEP5

Figure 7-47. eQEP Timing Requirements

7.9.5.8.2 eQEP Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

QEP6

td(QEP-CNTR)

Delay time, external clock to counter increment

For more information, see section Enhanced Quadrature Encoder Pulse (EQEP) Module in the device TRM.

7.9.5.9 GPIO

The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per

bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and

output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins))

pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this Device, general

purpose interface supports up to 242 pins.

For more details about features and additional description information on the device General-Purpose Interface,

see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Note

The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.

Table 7-38 presents timing conditions of the GPIO interface.

Table 7-38. GPIO Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.75

6.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

Section 7.9.5.9.1 and Section 7.9.5.9.2 present timings and switching characteristics of the GPIO Interface.

7.9.5.9.1 GPIO Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GP2

tw(GPIO_IN)

Minimum Input Pulse Width

3.6 + 2P(1)

(1)

P = functional clock period in ns.

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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