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STM32H723VG Datasheet(PDF) 191 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 191 Page - STMicroelectronics |
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191 / 227 page ![]() DS13313 Rev 2 191/227 STM32H723xE/G Electrical characteristics 208 Figure 46. USART timing diagram in Master mode 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 47. USART timing diagram in Slave mode MSv65386V1 CPHA=0 TX OUTPUT RX INPUT CPHA=0 LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK)/tf(SCK) th(RX) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(RX) tv(TX) th(TX) MSB IN BIT6 IN MSB OUT MSv65387V1 NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 TX output RX input tsu(RX) th(RX) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(NSS) tdis(TX) tsu(NSS) ta(TX) tv(TX) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(TX) tf(SCK) Last bit IN |
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